articleJan 1, 2003Closed access

Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction

RKRakesh KumarKIKeith I. FarkasNPNorman P. JouppiPRParthasarathy RanganathanDMDean M. Tullsen

Abstract

This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cores representing different points in the power/performance design space; during an application’s execution, system software dynamically chooses the most appropriate core to meet specific performance and power requirements. Our evaluation of this architecture shows significant energy benefits. For an objective function that optimizes for energy efficiency with a tight performance threshold, for 14 SPEC benchmarks, our results indicate a 39 % average energy reduction while only sacrificing 3 % in performance. An objective function that…

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677
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Authors

5
  • RK
    Rakesh KumarCorresponding
  • KI
    Keith I. Farkas
  • NP
    Norman P. Jouppi
  • PR
    Parthasarathy Ranganathan
  • DM
    Dean M. Tullsen

Topics & keywords

Keywords
  • Computer science
  • Frequency scaling
  • Reduction (mathematics)
  • Multi-core processor
  • Efficient energy use
  • Power (physics)
  • Dissipation
  • Design space exploration
UN Sustainable Development Goals
  • Affordable and clean energy
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