articleDigest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits ConferenceFeb 1, 2007Closed access
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
Linköping University · Intel (United States)
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Abstract
A 275mm 2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
Citation impact
634
total citations
- FWCI
- 108.07
- Percentile
- 100%
- References
- 7
Citations per year
Authors
14Topics & keywords
Topics
Keywords
- CMOS
- Chip
- Transistor
- Tile
- Computer science
- Network packet
- Network on a chip
- Die (integrated circuit)
UN Sustainable Development Goals
- Affordable and clean energy
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