ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration

As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. ORION [29] was amongst the first NoC power models released, and has since been fairly widely used for early-stage power es-timation of NoCs. However, when validated against recent NoC prototypes – the Intel 80-core Teraflops chip and the Intel Scal-able Communications Core (SCC) chip – we saw significant de-viation that can lead to erroneous NoC design choices. This prompted our development of ORION 2.0, an extensive enhance-ment of the original ORION models…