Low-Power CMOS Digital Design

Abstract—Motivated by emerging battery-operated applica-tions that demand intensive computation in portable environ-ments, techniques are investigated which reduce power con-sumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power opera-tion are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimization. An architectural-based scaling strategy is pre-sented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This op-timum is achieved by trading increased silicon area for reduced power consumption. I.