articleMicroelectronics JournalMay 3, 2016HYBRID OA

ASAP7: A 7-nm finFET predictive process design kit

Arizona State University · American Rock Mechanics Association

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Abstract

We describe a 7-nm predictive process design kit (PDK) called the ASAP7 PDK, developed in collaboration with ARM Ltd. for academic use. The PDK is realistic, based on current assumptions for the 7-nm technology node, but is not tied to any specific foundry. The initial version assumes EUV lithography for key layers, a decision based on its present near cost-effectiveness and resulting simpler layout rules. Non-EUV layers assume appropriate multiple patterning schemes, i.e., self-aligned quadruple patterning (SAQP), self-aligned double patterning (SADP) or litho-etch litho-etch (LELE), based on 193-nm optical immersion lithography. The specific design rule derivation is explained for key layers at the front end…

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Authors

8

Topics & keywords

Keywords
  • Back end of line
  • NMOS logic
  • PMOS logic
  • Static random-access memory
  • Transistor
  • Lithography
  • Multiple patterning
  • Schematic
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