Van der Waals polarity-engineered 3D integration of 2D complementary logic

Abstract Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis 1–3 . Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures 4,5 , as well as hetero-2D layers with different carrier types 6–8 , have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe 2 (refs. 9–17 ) and MoS 2 (refs. 11,18–28 )) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition…